1. Field of the Invention
The present invention relates generally to integrated circuit tester apparatus. More particularly, the present invention relates to test circuitry which may be configured on a single test chip or active probe card for performing tests on integrated circuits at speed.
2. Brief description of the Prior Art
As integrated circuits (ICs) become more and more complicated, testing also becomes more complex. Generally, ICs may be tested at the die level, the package level and the board level. However, most attention is given to testing at the board level since testing of the assembled product (i.e., a printed circuit board constructed from a collection of digital integrated circuits) is most critical. The test problem at the board level addresses three concerns: (1) confirmation that each component performs its required function; (2) confirmation that the components are interconnected in the correct manner; and (3) confirmation that the components in the assembled product interact correctly and that the product performs its intended function.
To facilitate testing the Institute of Electrical Electronic Engineers (IEEE) promulgated the IEEE Standard Test Access Port and Boundary Scan Architecture, as described in the document IEEE Standard 1149.1. The standard was developed by the Joint Test Action Group (JTAG) and has become known in the integrated circuit industry as the JTAG standard. The standard was aimed at easing board tests.
The IEEE Standard 1149.1 enables integrated circuits to be tested using boundary-scan methodology after the integrated circuits have been permanently installed on a circuit board. The specified JTAG standard circuitry may be incorporated into a probe card to create an active probe card for die level tests. Further, the specified JTAG standard circuitry may be incorporated into an adapter socket to perform tests at the package level for integrated circuits which lack internal test circuitry and which are assembled on a printed circuit board designed for integrated circuits having built-in IEEE 1149.1 standard test circuitry.
A disadvantage with the JTAG standard circuitry is that it is limited to low speed tests since the speed of data along the test bus runs at about 20 MHz. Integrated circuits which operate at speeds of 100 MHz and above are becoming more common and it is desirable to test these devices at their operating speeds rather than at a low speed for several reasons.
First, it is difficult to test for all the critical pathways of a high performance at low speed. This is especially true for a device under test which has a high number of inputs and outputs, since testing at low speed first requires that all possible pathway combinations between the input and outputs of the device be identified and measured, from this information the critical pathways (i.e., a pathway between an input and an output by which a signal must travel before some other event occurs) must then be determined. Also, since propagation delays do not vary as a function of speed, a test will fail for a device which is tested at a slower speed for which it is rated. In contrast, since testing a device at speed confirms the function of the device, all the critical paths between the inputs and outputs of a device are automatically measured.
Further, for low speed tests of a high performance device, the test will likely fail to verify all the critical pathways, since one or more of the pathways may be interrupted by an internal register which would hold the signal in the pathway for an indefinite amount of time. At present, the preferred way to measure a critical pathway which is interrupted by an internal register is by using an electron beam prober. However, this technique requires knowledge of the location of the register layout within the device under test and electron beam probers are very expensive.
Further still, low speed tests will not detect the simultaneous switching output which indicates a defective device. Simultaneous switching noise is not likely to be generated at low speeds since the stray capacitance and inductance are more pronounced at high speeds. Simultaneous switching noise indicative of a bad device becomes very noticeable during an at speed test.
While the benefits of testing integrated circuits at speed as opposed to testing at a low speed test are well understood, current state of the art high speed test such as the Hewlett Packard model 83000 and the Avanttest models T3681 and T3683 are very expensive.
U.S. Pat. No. 5,056,093 issued to Whetsel discloses a system scan path architecture using the IEEE proposed standard test bus 1149.1. In Whetsel the architecture comprises a plurality of printed circuit boards each having a device select module (DSM) connected in daisy chain fashion with a series of primary and secondary scan paths. The DSMs include four ports for connection with the IEEE standard test bus. Whetsel teaches to reduce the overall test time by configuring the DSMs to select a desired scan path on a board or boards such that all nonessential secondary scan paths within each boundary scan region are not traversed. This arrangement permits independent control of testing selected scan paths without using the bypass mode of the IEEE 1149.1 test standard architecture. While a reduction in the overall test time may be achieved by the selective coupling of scan paths to the IEEE test bus, the actual test rate in Whetsel is limited to the speed of the IEEE test bus and the length of the longest path.
In addition to the boundary-scan techniques and related IEEE standard boundary-scan architecture for testing integrated circuits, it is known from the prior art to design integrated circuits with internal scan test capability.
For example, U.S. Pat. No. 4,931,722 issued to Stoica discloses a flexible imbedded test system for VLSI circuits wherein a logic chip is designed with a plurality of scan chains, wherein each scan chain contains a number of flip flops. The flip flop chains may be serially scanned or operate in parallel such that selected combinational logic units may be bypassed. Stoica teaches to operate the flip flop chains in a parallel manner for internal test purposes of the chip to reduce the total test time of the logic chip to the amount of time it takes to test the longest chain of flip flops in the logic chip.
The internal scan test approach of Stoica is complimentary rather than a substitution for the standardized boundary-scan approach for testing ICs. However, even if the two approaches were combined for a signal comprehensive IC test procedure, there would still exist the low speed test limitations associated with the standard test bus. Accordingly, there is a definite need in the art for a boundary-scan test architecture which may be in accordance with the IEEE 1149.1 standard and which permits testing IC devices at speed such that functional testing of the ICs may be accomplished